Random defect yield analysis of a semiconductor chip without a built-in redundancy scheme is complex, but straightforward. The failure model is the same for the entire chip. If a failure due to a random defect occurs anywhere on the chip, the chip fails. Therefore, every section of area on a chip without a built-in redundancy scheme directly impacts the yield simulation result.
A chip with a built-in redundancy scheme complicates the yield simulation because defects may not cause failures. An example is a memory chip. If a failure due to a random defect occurs in a region of the memory chip that has no redundancy, the chip fails. However, if a random defect occurs in a region of the memory chip that has a redundancy scheme, such as a single bit in the array, the chip does not necessarily fail. Therefore, the failure model for a chip with built-in redundancy is different and more complex due to the redundancy scheme.
The necessity of a different failure model for chips with specific circuits is analogous to the design rule check (DRC) landscape where there are specific design rules for specific regions or circuits. For example, there are specific design rules for electrostatic discharge (ESD) devices and systems, or SRAM array cells. In the same way, random defect yield simulation requires new failure models to accurately calculate a yield simulation result for chips with built-in redundancy schemes.